1. Field of the Invention
The present invention relates to charge coupled devices (CCD) typically used to capture color pictures in digital form, and more specifically to a method and apparatus for controlling the range and resolution of the offset applied to the output of the CCDs.
2. Related Art
Charge coupled devices (CCDs) are often used to capture images received in the form of light. A CCD typically contains several pixels, with each pixel holding an amount of charge proportionate to the intensity of incident light and the length of time the light is allowed to fall on the pixel. The charge can be later translated to a voltage level and/or digital data for further processing and/or storing (in mass non-volatile storage). CCDs thus find application in devices such as digital cameras and scanners as is well known in the relevant arts.
A correction (termed xe2x80x9coffset correctionxe2x80x9d) is often applied to the output (i.e., voltage or digital data in the above paragraph) of a CCD typically to compensate for (or eliminate) undesirable components which may be present in the CCD output. For example, the charge generated by a CCD should ideally be entirely generated by the incident light but other phenomenon such as thermally generated electron-hole pairs add to the charge.
Such additions are undesirable, for example, because a later reproduced image may be brighter than that represented by the light incident on the CCD. Accordingly, it is desirable that the undesirable components be eliminated, and the corresponding correction is termed as offset correction. The extent to which a correction is applied, is referred to as an offset, and the act of applying the offset to the CCD output may be referred to as offset correction.
It is often desirable to control the correction range and resolution of the offset correction. The correction range refers to the maximum voltage correction (assuming zero voltage to be the minimum) that may be attained by the operation of various components of an offset correction circuit. Resolution refers to the minimum amount of correction of the output voltage that can be attained by the offset correction circuit.
However, such control may need to be achieved without introducing further undesirable components into the CCD output and/or increasing substantially the electrical power consumption in the process.
An aspect of the present invention provides a designer the ability to control the correction range and to attain low correction resolution while minimizing the introduction of additional undesirable components (noise) in the CCD output voltages. The introduction of noise can generally be minimized by minimizing the number of stages in the correction circuit. Minimizing the number of stages has the additional benefit of reducing power consumption requirements.
In one embodiment, only two stages are required to achieve desired gain. Correlated double sampling operation is performed in the first stage while attaining some amount of gain. The second stage is used to attain the remainder of the desired gain using a programmable gain amplifier (PGA). While the described embodiments contain only two stages, it should be understood that several aspects of the present invention can be implemented using a different number of stages.
Offset correction is attained by using two digital to analog converters (DAC), with each DAC controlling the correction in one stage. The first DAC is referred to as the coarse DAC (CDAC) which is connected to a correlation double sampler (CDS) located in the first stage. The second DAC is referred to as a fine DAC (FDAC), and is connected to the PGA in the second stage. While a solution could be implemented using only a single DAC, the same would typically require a DAC of very high resolution, which provides challenges in implementation and would normally consume more power.
CDS may be implemented to amplify the input signal (voltage from the CCD) while partially correcting the signal. The correction may be controlled by a first capacitor (Ccdac) driven by the CDAC. The input signal may be received via a second capacitor (Csinp). The second input of both the first capacitor and the second capacitor are coupled to a feedback capacitor (Cfcds) implemented in conjunction with the CCD.
As would be readily appreciated, the gain of the input signal component (as present at the output of the CCD) is determined by the ratio Csinp/Cfcds. Assuming that the voltage applied at the output of CDAC equal Vcdac and that the input voltage equals Vi, the total output (Vcds) of the CCD equals ((Vi*Csinp/Cfcds)xe2x88x92(Vcdac*Ccdac/Cfcds)), wherein xe2x80x98*xe2x80x99 represents a multiplication operation. The capacitors and their capacitance values are represented by the same reference labels in the present application.
According to an aspect of the present invention, the ratio of Ccdac to Csinp is maintained to be a constant, which allows the offset effected to be independent of the voltage level Vi. The need for such independence may be appreciated by first understanding that it may be desirable to amplify the input signals to a degree which is inversely proportionate to the maximum possible amplitude (or range, if minimum is not equal to zero) of the input signal. Typically, the ratio of Ccdac/Cfcds is controlled to attain the desired amplification of the input signal in the first stage. By maintaining Ccdac/Csinp to be a constant, the offset correction due to the first stage can be determined by Vcdac, which in turn is determined by a numerical input to CDAC.
The output of the CDS may be connected to a capacitor Cspga, which in turn is corrected to the PGA of the second stage. Offset correction is further effected by a capacitor (Cfdac) driven by a fine DAC (FDAC). The second input of both Cspga and Cfdac is connected to a feedback capacitor (Cfpga) associated with the PGA. The output of PGA (Vpga) may be given by the equation ((Vcds*Cspga/Cfpga)xe2x88x92(Vfdac*Cfdac/Cfpga)), wherein Vfdac represents the output voltage of the FDAC.
According to another aspect of the present invention, the ratio of Cfdac to Cfpga is maintained to be a constant, which allows the correction resolution to potentially equal a least significant bit of an ADC (used to sample the output of the PGA). That is, the present invention allows offset correction to be effected by minute (small) amounts limited only by the resolution of a later sampling ADC.
Thus, once total desired amplification of the input signal (Vi) is determined, partial amplifications for each of the two stages may be assigned. The capacitances (Csinp, Cspga, Cfpga and Cfcds) may be configured consistent with the assigned partial amplifications. The capacitances Ccdac and Cfdac may be configured consistent with the objectives noted above with reference to correction range and correction resolution. By using the features of the present invention, offset correction, which quickly removes (at least substantially) the undesirable components, may be implemented.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.